Non-volatile memory (NVM) is able to retain data when the power supply of a memory is cut off. The memory can be used to store data such as parameters, configuration settings, long-term data storage, etc. Similarly, this kind of memory can be used to store instructions, or codes, for microprocessors, DSPs, or microcontrollers (MCU), etc. Non-volatile has three operations, read, write (or called program), and erase, for reading data, programming data, and erasing data before re-programming. Non-volatile memory can be a flash memory that can be programmed from 10K to 100K times, or Multiple-Time Programmable (MTP) that can be programmed from a few times to a few hundred times.
One-Time-Programmable (OTP) is a particular type of non-volatile memory that can be programmed only once. An OTP memory allows the memory cells being programmed once and only once in their lifetime. OTP is generally based on standard CMOS process and usually embedded into an integrated circuit that allows each die in a wafer to be customized. There are many applications for OTP, such as memory repair, device trimming, configuration parameters, chip ID, security key, feature select, and PROM, etc.
FIG. 1 shows a conventional OTP cell. The OTP cell 10 has an OTP element 11 and a program selector 12. The OTP element is coupled to a supply voltage V+ in one end and a program selector 12 at the other. The program selector 12 has the other end coupled to a second supply voltage V−. The program selector 12 can be turned on by asserting a control terminal Sel. The program selector 12 is usually constructed from a MOS device. The OTP element 11 is usually an electrical fuse based on polysilicon or silicided polysilicon, a floating gate to store charges, or an anti-fuse based on gate oxide breakdown, etc.
FIG. 2 shows a pin configuration of a conventional serial OTP memory 20. The OTP memory 20 has an OTP memory module 22 and a power-switch device 21 that couples to a high voltage supply VDDP and the OTP memory module 22. The OTP memory 22 has a chip enable, program, clock, power-switch select, and an output signal denoted as CS#, PGM, CLK, PSWS, and Q, respectively. CS# selects the OTP memory 22 for either read or program. PGM is for program or read control. CLK is for clocking the memory 22. PSWS is for turning on an optional device, power-switch device 21. The output signal Q is for outputting data. Since there are several I/O pins, the footprint of an OTP memory to be integrated into an integrated circuit is large and the cost is relatively high.
FIG. 3(a) shows a program timing waveform of a serial OTP memory with the I/O pin configurations as shown in FIG. 2. If the CLK is low and PGM is high when the CS# falls, the OTP goes into a program mode. Then, PGM toggles to high before the rising edges of CLK for those bits to be programmed. The high CLK period is the actual program time. Similarly, FIG. 3(b) shows a read timing waveform of a serial OTP memory with the I/O pin configurations shown in FIG. 2. If the CLK is high and PGM is low when CS# falls, the OTP goes into a read mode. The cell data are read out at the falling edges of CLK one by one. These timing waveforms in FIGS. 3(a) and 3(b) are relatively complicated.
Another similar low-pin-count I/O interface is the Serial Peripheral Interconnect (SPI) that has CSB, SCLK, SIN, and SO pins for chip select, serial clock, serial input, and serial output, respectively. The timing waveform of SPI is similar to that in FIGS. 3(a) and 3(b). Another two-pin serial I/O interface is I2C that has only two pins: SDA and SCL, for serial data and serial clock, respectively. This I/O interface is for an SRAM-like devices that have comparable read and write access time. The I2C for programming a byte or a page in a serial EEPROM is quite complicated: upon issuing a start bit, device ID, program bit, start address, and stop bit, the chip goes into hibernation so that an internally generated programming is performed for about 4 ms. A status register can be checked periodically for completion before next program command can be issued again. In an OTP, the program time is several orders of magnitude higher than the read access and much lower than either the program or erase time of EEPROM, for example 1 us versus 50 ns for read and 1 us versus 4 ms for program/erase, such that I2C interface for OTP is not desirable because of high timing overhead.
As OTP memory sizes continue to be reduced, the number of external interface pins becomes a limitation to the OTP memory size. The current serial interfaces have about 2-5 pins and are not able to effectively accommodate read and program speed discrepancies. Accordingly, there is a need for a low-pin-count interface for non-volatile memory, such as OTP memory.
As integrated circuits reach the limit of scaling in monolithic chips, stacking ICs into a vertical direction becomes a natural choice. When dies are stacked into the third dimension, the so-called “3D IC,” OTP memory becomes more important for defect redundancy, device trimming, configuration storage, and parameter adjustments to fix any manufacturing defects or performance degradation during 3D IC processing. In a 3D IC package, bare dies are ground and thinned down from 100 um to about 5-25 um and then stacked on top of each other on a substrate or interposer. At least one Through Silicon Vias (TSV), with diameters in the range of 5-50 um, are drilled through multiple dies for interconnect. A substrate or interposer can be used to support the dies or as a media for interconnecting these dies together.
During the 3D IC processing, some manufacturing defects can be generated to degrade yields, such as particle, contamination, or stress. New failure bits can easily be created in the memory dies. For example, if DRAM can be repaired again after IC package, 2% of yield can be saved. Moreover, thinning down the wafers from 100 um to 5-25 um or less can create stresses in silicon, and further, changing the silicon properties. The stress can affect the device characteristics, such as threshold voltage, leakage, silicon bandgap, or driving capability. The stress can also increase device mismatch and degrade analog performance substantially. For example, any new stress and/or mismatch created can easily affect the performance of A/D, D/A, amplifier, or bandgap reference. For logic chips, changing device performance can affect the relative timing such that clock setup time or hold time can be violated after 3D IC processing. As a result, the 3D IC may not be functional. Different 3D ICs can have different I/O configurations, such as different I/O numbers, I/O termination, I/O driver strength, and I/O capacitive coupling for customization. The configuration settings can vary from one 3D IC to others that need to be stored for tracking.
As more dies are stacked into 3D ICs, manufacturing defects, device trimming, parameter adjustments are needed to tailor for different 3D IC configurations. As a result, there is a need to invent a more systematic approach to improve the yield and performance of a 3D IC by using low-pin-count NVMs, especially low-pin-count OTP memories, much more creatively after the 3D ICs are fabricated.